Researchers at the University of Texas at Austin, Yale University and Texas State University have been awarded $5 million by the Defense Advanced Research Projects Agency (DARPA) as part of a program designed to spark the next wave of semiconductor innovation and circuit design in the U.S.

An "Asynchronous FPGA chip" built using the tools Keshav Pingali and his collaborators are developing for DARPA.

The UT Austin team is led by Keshav Pingali, the W.A."Tex" Moncrief Chair in the Institute for Computational Engineering and Sciences(ICES), and a professor in the Department of Computer Science and Department of Electrical and Computer Engineering.

The overall goal of DARPA's IDEA/POSH program is to greatly reduce the resources, expertise and time it takes to develop new chips. Demand for System-on-Chip (SoC) platforms has remained strong but the cost to design these platforms has increased to a point where smaller companies often do not have the resources to design these circuits for specialized applications. That leaves it to a few large corporations to fill the demand - and little room for innovation.

To correct that, DARPA formed the Electronics Resurgence Initiative (ERI), which brings together researchers from academia, commercial industry, and the defense industrial base to address today's SoC design complexity and cost barriers. The IDEA/POSH program is one of several programs started by DARPA under this initiative.

UT Austin will receive a total of $1.7 million over four years.

Pingali's group will work with Yale and Texas State to develop parallel electronic design automation (EDA) software for building computer chips. He says that the proposed software will be unique in several ways.

First, the tools will target both synchronous and asynchronous circuit designs. Systems with synchronous circuits are the industry standard but with this approach, a system can run only as fast as the slowest function that is supported. Systems with asynchronous circuits on the other hand allow each function as little or as much time as needed to complete its task, so the system works more efficiently taking only as much time as necessary rather than the time taken by the slowest function. The new project will address the needs of both communities.

Second, the software will be designed to run on multicore and manycore parallel processors, including processors with graphics processing units.

"Chip designs have become so complex that the only way to shorten design cycles is to exploit parallel computing," Pingali said.

In previous research funded by DARPA and NSF, Pingali's center developed a parallel programming system called Galois, which makes it easier to write parallel software for multicore and manycore platforms. This system will play a key role in the new project.

"The EDA industry has recognized the need to parallelize their software for a while now," Pingali said, "and they refer to this as EDA 3.0. Our new project brings together experts in EDA tools and parallel computing to make EDA 3.0 happen."

For more information, contact: Marc Airhart, College of Natural Sciences, 512-232-1066.