PerfExpert: A Simple, Automatic Performance Assessment Tool for Programs Running on Multi-core Computers

Computing & Wireless : Application Software

Available for licensing


  • Martin Burtscher, Ph.D. , ICES
  • James Browne, Ph.D. , Computer Science

Background/unmet need

Most application programs do not reap the full performance benefit of the underlying hardware. Emerging multi-core and multi-socket systems greatly increase the already high dimensionality and complexity of performance optimization. Performance optimization requires not only identification of code segments that are performance bottlenecks but also characterization of the causes of the bottlenecks and determination of code restructurings that will improve performance.

While identification of possible performance bottlenecks can be accomplished with simple timers, characterization of the cause of the bottleneck requires much more sophisticated measurements.

Invention Description

This invention is a software tool that automatically evaluates the performance of a program running on one or more cores, multi-core chips, or multichip nodes. It indentifies possible performance bottlenecks at the source-code level (functions and loops). The tool then states the likely causes and suggests possible solutions for alleviating each bottleneck in a manner that can be easily understood by programmers.


  • Simplifies and accelerates the software performance evaluation process
  • Completely automates bottleneck identification and analysis
  • Recommends possible optimizations for each type of bottleneck
  • Makes performance evaluation feasible for programmers who are not performance experts by eliminating requirement for knowledge about chip architectures and compilation methods


  • Open-source implementation (Linux)
  • Focuses on optimization of multi-core chip and multi-chip performance.
  • Analytics based on novel performance metric: local cycles per instruction (LCPI)

Market potential/applications

Performance-critical software for systems with multi-core chips or multi-chip nodes.

Development Stage

Beta product/commercial prototype