Method and Apparatus for Capacitance Multiplication Within a Phase-Locked Loop

Computing & Wireless : Hardware

Available for non-exclusive licensing


  • Earl Swartzlander, Jr., Ph.D. , Electrical and Computer Engineering
  • Moises Robinson , Xilinx
  • Marwan Hassoun , Xilinx

Background/unmet need

Often phase-locked loops are used to filter phase noise and jitter from a reference clock. These are referred to as “clean-up ” phase-locked loops. They require large values of capacitance to achieve a low loop bandwidth. Traditionally the large values of capacitance are realized with physically large on-chip capacitors or with discrete capacitors off-chip. Both of these are undesirable: on-chip capacitors may require 1 square mm of chip area which is prohibitively expensive, and off-chip capacitors require using precious package pins and use circuit board area.

Invention Description

The method and apparatus of the invention uses two charge pumps to multiply the apparent capacitance of a physically small on-chip capacitor to appear to be a much larger value of capacitance which is used within the phase-locked loop circuit to provide a very low bandwidth, thereby reducing the phase noise and random jitter of a clock signal.


    A chip area of approximately 100 μm by 100 μm can realize two 50 pF physical capacitors that can be multiplied to make two capacitors with an apparent capacitance of 10 nF each. Without the invention it would take an area of about 2 square mm to realize the capacitors. The invention reduces the area by a factor of about 200.

Market potential/applications

”Clean-up ” phase-locked loops, low bandwidth analog filters

Development Stage

Proof of concept

IP Status

  • 3 foreign patents application filed
  • 1 U.S. patent issued: 7,307,460