Bridged, Three-Path Fused Multiply-Adder
Computing & Wireless : Hardware
Available for non-exclusive licensing
- Earl Swartzlander, Jr., Ph.D. , Electrical and Computer Engineering
- Eric Quinnell , Electrical and Computer Engineering
- Carl Lemonds , Advanced Micro Devices, Inc. (AMD)
Industry floating-point fused multiply-adders (FMA) to date all use a slight derivation of the original FMA serial architecture. Classically this architecture is subject to two major tradeoffs: 1) difficulty in implementation due to massive alignment and end-around-carry components—especially in the face of wire-dominant 65nm and smaller technologies; and 2) the floating-point unit (FPU) architecture faces both a loss of performance due to a reduction in parallel single instruction addition and multiplication capabilities as well as an increase in overall complication by switching to a three-operand datapath interface.
The Bridge and Three-Path FMA architectures provide two unique solutions to the major tradeoffs seen by classic FMA designs. The Three-Path architecture provides a solution to the massive alignment and component size implementations of the classic FMA by using three mutually exclusive hardware paths that carve out different major arithmetic cases of the internal FMA datapath—allowing for not only a reduction in component size, but also a reduction in latency, a reduction in power, and a model that scales well with smaller technologies. The Bridge FMA architecture provides a solution to the second major tradeoff of the classic FMA by presenting a simple architectural improvement that may be integrated into existing floating-point units without deteriorating the performance of single additions and multiplications or requiring a complete structural overhaul of the machine.
- The Three-Path architecture reduces latency and power as compared to a classic FMA industrial unit by using mutually exclusive hardware paths that selectively power on and off based on the required arithmetic case.
- The Bridge architecture adds FMA capability to existing floating point units at a relatively low area cost and without forcing a reduction in the parallel instruction capabilities or needing a major overhaul of the entire FPU structure.
Processor design, floating-point design, computer architecture, 3D graphics, video processing, digital signal processing (DSP), computer arithmetic, computer division, Fast Fourier Transform (FFT), transcendental calculation, multimedia applications.
Proof of concept
- 1 U.S. patent issued: 8,078,660