Multipliers Implemented Using Memristor Gates

Computing & Wireless : Computing Methods

Available for licensing

Inventors

  • Earl Swartzlander, Jr., Ph.D. , Electrical and Computer Engineering
  • Lauren Guckert , Electrical and Computer Engineering

Background/unmet need

Memristors are an emerging semiconductor technology. They are small in size and can operate at high clock rates. They are capable of storing values and performing logic. The Memristors As Drivers gates (MAD gates, for short) are the most efficient of the various memristor logic approaches. This patent discloses a variety of multipliers implemented with MAD gates. 

In this work, new designs for memristor-based multipliers are presented. The proposed designs include shift-and-add multipliers, Booth multipliers, array multipliers, and Dadda multipliers. Some of these designs are the first implementation of its kind using memristors.

Invention Description

These memristor based multipliers are much more efficient than conventional CMOS or memristor-CMOS hybrid techniques.

In contrast to other memristor implementations of logic, MAD gates can support high fan-out and require a single cycle for any of the common two-operand logic functions. This facilitates the efficient implementation of digital multipliers. They also reduce the need to data movement and help maximize parallelism in the system. 

Benefits/Advantages

    These memristor multipliers are smaller and faster than other multipliers. They can also exist in logic-in-memory applications. 

Features

  • These multipliers employ MAD gates, which require less than half the number of delay steps of traditional CMOS implementations of multipliers. The area is also quite small.
  • The total delay of the MAD design is less than half as many steps as the CMOS and almost all other implementations. Also, it requires fewer memristors and drivers than all of the other proposed designs and less than 20% the number of components of CMOS. The multiplier can also be pipelined to complete an N-bit addition every 4 steps at maximum throughput. Traditional CMOS designs and most memristor-based designs do not inherently support pipelining. 
  • Similarly, for array multipliers, the MAD gate requires the fewest components and has the fastest delay. The delay is one-third the number of steps in CMOS.

Market potential/applications

The use of multipliers implemented with memristors (specifically MAD gates) will improve the speed and complexity of a wide variety of arithmetic operations, including in Big Data and machine learning applications. As our research continues, we will be developing numerous other arithmetic units including a wide variety of dividers. 

IP Status

  • 1 U.S. patent application filed