Noise and Spur Reduction Technique in Fractional-N PLL
Physical Sciences : Electrical
Available for licensing
- Nan Sun, Ph.D. , Electrical & Computer Engineering
Delta Sigma fractional-N phase-locked loop (PLL) plays an important role in modern electronic systems. Contrary to integer-N PLLs, fractional-N PLLs allow synthesis of frequencies which are a fraction of the reference frequency. Thus, a fractional-N PLL can use a higher reference frequency than an integer-N PLL for the same frequency resolution. It allows a wider PLL bandwidth, which leads to faster settling time and stronger suppression of VCO noise.
However, Delta Sigma fractional-N PLLs have an additional noise source in the form of quantization noise from the Delta Sigma modulator used to generate the fractional division ratio. For a wide-band PLL, the quantization noise can easily dominate the PLL phase noise.
There have been several approaches to address this issue. An analog approach is to inject current into the charge pump to cancel out the instantaneous phase error due to Delta Sigma quantization noise. However, this approach requires a very high resolution digital-to-analog converter (DAC) along with accurate gain and offset calibration techniques.
A multi-phase ring VCO can be used to cancel the instantaneous phase error, but it requires complicated phase realignment technique. Another mostly digital approach is to use an FIR filter at the output of the 1-bit Delta Sigma modulator to reduce the quantization noise, but it is effective only at high frequencies. For a wide-band PLL, a large number of FIR filter taps are required to adequately suppress the quantization noise.
Researchers at The University of Texas at Austin have developed a simple, effective, and mostly digital technique to reduce the Delta Sigma quantization noise of phase-locked loop (PLL) at all frequencies. The proposed technique achieves a significant improvement in performance over the conventional technique as well as the FIR filtering technique while incurring only a small increase in hardware complexity.
It greatly reduces fractional-N quantization noise and spur.
It has a unique fractional-N PLL architecture.
Any company that needs high accuracy clock generation circuit will be interested.
Proof of concept
- 1 U.S. patent application filed