Tailoring atomic layer deposition growth across features using self-assembled monolayers

Physical Sciences : Materials and Compounds

Available for licensing


  • John Ekerdt, Ph.D. , Chemical Engineering
  • Sonali Chopra, B.S. , Nascent

Background/unmet need

Etching and lithography comprise the majority of the cost in fabrication of computer chips. Lithography requires costly light sources to achieve optimal resolution, and pattern alignment errors can become a critical yield killer as feature sizes decrease. In contrast, a chemical approach avoids a need for some pattern alignment steps. Etching requires very careful control of process parameters to achieve good selectivity and anisotropy, and as features decrease it becomes increasingly difficult to maintain shape, particularly for heterostructured layers.

Area-selective atomic layer deposition (AS-ALD) is a technique that has been previously shown to reduce the number of lithographic and etching steps required during fabrication. ALD is a deposition technique that offers precise thickness control to less than one nanometer, high conformality over features, and the ability to deposit materials at low temperatures. Applying the AS-ALD methodology to surfaces that already have features requires careful attention to surface chemistry as well as surface energy and roughness effects introduced by the areas of curvature.

Invention Description

Researchers at The University of Texas at Austin developed a novel method to tailor the sites for growth on surfaces with curvature when using atomic layer deposition. The results of this process can be seen in the cross-sectional TEM-EDS (transmission electron microscopy-energy dispersive X-ray spectroscopy) image below. The brighter red regions in the Ti elemental scan indicate areas of higher concentration.


  • Reduction of fabrication requirements for nanoscale structures
  • Promise of yield enhancement
  • Reduction in etching and lithography costs


  • Selectively deposit a conductive film on desired regions of a planar substrate
  • Tailor growth of a conductive film on a substrate with curvature

Market potential/applications

Semiconductor/microelectronic fabrication companies

Development Stage

Proof of concept

IP Status