Method for Passive Alignment of Semiconductor Wafers

Nanotechnologies : Physical Science Apps

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Inventors

  • Michael Cullinan, Ph.D. , Mechanical Engineering, Cockrell
  • Andrew Duenner, BBA , Mechanical Engineering

Background/unmet need

Recent advancements in metrology and nanofabrication systems have created a demand for wafer alignment mechanisms with positioning repeatability on the order of microns to tens of microns. Current methods for passive wafer alignment are time-consuming, inaccurate, or impractical. Optical alignment systems are time-consuming to use. Alignment systems that rely on MEMS-based structures on the wafer are impractical for most applications. Current alignment mechanisms that use pin constraints have a tendency to jam.

Invention Description

A novel method has been developed for rapid and repeatable passive alignment of silicon wafers. The method is based on three pins which keep the wafer constrained and a nesting force which keeps the wafer in contact with the pins, and consists of a number of features that minimize the probability of wafer jamming and maximize wafer positioning repeatability. This process has been shown to be capable of positioning repeatability on the order of 1 micron with a setup time less than thirty seconds.

Benefits/Advantages

  • Reduces precision required by wafer manipulators and handlers
  • Minimizes probability of wafer jamming
  • Supports in-line wafer metrology and semiconductor manufacturing
  • Repeatability better than ten microns

Features

  • Simple and low-cost mechanism that can easily be integrated into manufacturing processes
  • Compatible for fixturing and aligning a wide variety of shapes
  • Completely passive design does not require controls or electronics
  • Adjustable and precise force application
  • Micron-scale positioning accuracy

Market potential/applications

Semiconductor fabrication; wafer metrology

Development Stage

Lab/bench prototype

IP Status

  • 1 U.S. patent application filed