Statistical estimation based noise reduction technique for low power SAR ADC design

Physical Sciences : Electrical

Available for licensing

Inventors

  • Nan Sun, Ph.D. , Electrical & Computer Engineering
  • Long Chen , Electrical & Computer Eng
  • Xiyuan Tang , Electrical & Computer Engineering

Background/unmet need

A successive approximation analog-to-digital converter is used to digitize the physical analog signals to logic digital signals. It often requires low noise to achieve high accuracy. Traditionally the low noise is realized by utilizing a large comparator or averaging. Those methods are not desirable since large comparator is power hungry and averaging accuracy is not high.

Invention Description

The technique of the invention presents a power-efficient SNR enhancement technique for SAR ADCs. By accurately estimating the conversion residue, it can suppress both comparator noise and quantization error. Thus, it allows the use of a noisy low-power comparator and a relatively low-resolution DAC to achieve high resolution.

Benefits/Advantages

  • 7 dB increase in measured signal to noise ratio
  • Increased SNR with 2.5 times increased comparator power vs. 21 times via brute force

Features

  • Low hardware complexity
  • Requires no change to the standard ADC operation except for repeating LSB comparisons

Market potential/applications

Low power, high accuracy data converters; wearable electronics; wireless network sensors

Development Stage

Lab/bench prototype

IP Status