Cap Layer for Extrusion Reduction in Through Silicon Vias for 3D Integrated Circuits

Physical Sciences : Electrical

Available for licensing

Inventors

  • Paul Ho, Ph.D. , Mechanical Engineering
  • Tengfei Jiang , University of Texas at Austin

Background/unmet need

The through-silicon-via (TSV) is a critical element that provides short vertical interconnects in die stacks to improve the electrical performance, power consumption, and form factor for 3D integrated circuits. The mismatch of thermal expansion coefficients (CTE) between the Cu via and the Si wafer can induce significant thermal stresses that impact device performance, raising serious reliability concerns. Of particular concern is the Cu extrusion induced by thermal stresses, which can cause failure in the TSV and in the adjacent interconnect structures during fabrication or thermal cycling. This has been identified as a critical yield and reliability problem in manufacturing and operation of 3D integrated circuits.

Invention Description

A method and material developed by Prof. Paul Ho of the Department of Mechanical Engineering at UT Austin uses a cap layer on the TSV to reduce the Cu extrusion for yield and reliability improvement. This material and method can be readily implemented in the fabrication process of 3D interconnects.

The cap layer constitutes a thin metallic layer which can react with the Cu TSV underneath to form an alloying layer at the interface or partly dissolve into the Cu grain boundaries. This will reduce the interfacial and grain boundary mass transport and thus decrease the amount of TSV extrusion. Metals have to be chosen not only to fulfill this requirement but also have to be compatible with the Cu TSV fabrication process. The group has discovered a number of metals to be particularly effective with an average reduction of more than 50%. This reduction can significantly improve the yield and reliability of 3D integrated circuits.

Benefits/Advantages

  • Reduced interfacial and grain boundary mass transport between via Cu and silicon
  • More than 50% reduction of Cu extrusion during thermal cycling
  • Improved TSV reliability and 3D IC chip yield

Features

  • Proposed cap layer can be formed by standard deposition methods, compatible with present technology of TSV fabrication.
  • Deposition method is also compatible with the current BEOL process and can be incorporated easily into the BEOL process.
  • Method is applicable to other fabrication process, such as direct chip attachment.

Market potential/applications

Advanced 3D IC fabrication using TSV contacts; advanced direct chip or die mounting through Cu contacts

Development Stage

Proof of concept

IP Status

  • 1 U.S. patent application filed