Vertical III-V Nanowire FETs Using Nano-sphere lithography
Computing & Wireless : Hardware
Available for licensing
- Jack Lee, Ph.D. , Electrical and Computer Engineering
- Fei Xue, Ph.D.
As CMOS technology aggressively scales down and approaches its physical limitations, new materials and novel device structures are desired to enable further performance improvements. Vertical III-V nanowire FETs using nano-sphere lithography technique were invented for low-power logic MOSFET applications. By applying this device and process, improved current drive capacity, increased integration density, lower power consumption and reduced cost can be achieved.
In this invention, University of Texas at Austin researchers designed Field Emission Transistors utilizing vertical 3-D nanowire structure constructed with III-V group materials. This structure is realized by an innovative nano-sphere lithography method.
- Material: this device is built on III-V materials with better transport properties than silicon. In III-V materials, the electrons possess lower effective mass and higher mobility, leading to improved current drive capacity.
- Structure: 3-D nanowire structure is applied instead of planar MOSFETs. Nanowire structure optimizes electrostatic control compare to planar devices due to better gate coupling, which helps to reduce standby power consumption. Vertical nanowire structure also increases the integration density.
- Process: nano-sphere lithography is used for nano-pillar construction. By applying nano-sphere lithography technique, mask of conventional photo lithography is no longer needed, leading to reduced cost. Compared to nano-imprint, this process improve the throughput through simplified implementation.
- 3-D vertical nanowire structure
- Use of III-V materials in the FET design
- Use of nano-sphere lithography
High-performance IC designer and manufacturers
Proof of concept
- 1 U.S. patent issued: 9,209,271