Three-Dimensional InGaAs Gate-Wrap-Around Field-Effect-Transistor with Multiple Channel Layers

Computing & Wireless : Hardware

Available for non-exclusive licensing

Inventors

  • Jack Lee, Ph.D. , Electrical and Computer Engineering
  • Fei Xue, Ph.D.

Background/unmet need

As CMOS technology aggressively scales down and approaches its physical limitations, new materials and novel device structures are desired to enable further performance improvements. Three-dimensional InGaAs gate-wrap-around field-effect-transistor (GWAFET) with multiple channel layers stacked vertically are invented for low-power logic MOSFET applications, enabling further CMOS scaling. This device provides improved current drive capacity, increased integration density and lower power consumption.

Invention Description

 In this invention, University of Texas at Austin researchers designed an innovative approach to current CMOS scaling challenges utilizing 3-D gate-wrap-around structure, multi-channel layers and III-V materials.

Benefits/Advantages

  • MATERIALS: this device is built on III-V materials with better transport properties than silicon. In III-V materials, the electrons possess lower effective mass and higher mobility, leading to improved current drive capacity.
  • STRUCTURE 1: 3-D gate-wrap-around structure, instead of conventional planar MOSFET or FinFET structure, offers better electrostatic control due to gate coupling, which helps to reduce standby power consumption.
  • STRUCTURE 2: multiple channel layers provide higher current density because of vertically stacked channels. Vertical stacking does not increase the overall device size.

Features

  • Use of III-V materials in the FET design
  • 3-D wrap-around-gate structure
  • Vertically stacked multiple channel layers

Market potential/applications

High-performance IC designer and manufacturers  

Development Stage

Proof of concept

IP Status