Improved Fused Floating-Point Two-Term Dot Product Unit

Computing & Wireless : Computing Methods

Available for licensing


  • Earl Swartzlander, Jr., Ph.D. , Electrical and Computer Engineering
  • Jongwook Sohn, Ph.D. , Intel

Background/unmet need

Many computer graphics and digital signal processing (DSP) applications call for computation of the two-term dot product of four floating-point data. When the data are in the IEEE Std. 754 32-bit format, the floating-point multiplications and addition are difficult and time-consuming operations.

Invention Description

This invention presents improved architecture designs and implementations for a fused floating-point dot product unit. Many DSP applications such as FFT and DCT butterfly operations can benefit from the fused floating-point dot product unit. The fused floating-point dot product unit takes four normalized floating-point operands and generates the sum or difference of the two products. It supports all five rounding modes specified in IEEE-754 Standard. Several techniques are applied to achieve low area, low power consumption, and high speed.


  • Improved computing speed
  • Reduced rounding errors
  • Reduced processor area and power consumption


  • This invention avoids the rounding and normalization of "stand-alone" multiplies to reduce the latency, chip area, power consumption, and rounding errors.
  • A two-path addition algorithm is used to maximize the speed.
  • The pipelined implementation nearly triples throughput.

Market potential/applications

 Digital Signal Processing (DSP) that requires time-frequency transformation

Development Stage

Lab/bench prototype

IP Status